This invention relates to an improvement of an Insulated Gate Field Effect Transistor (IG FET), namely an MIS FET (Metal-Insulator-Semiconductor Field Effect Transistor).
The IG FET which is widely used as the major element of an integrated circuit preferably has high-spaced operational characteristics and a small occupation area in order to meet the requirements of a high-performance integrated circuit. In existing IG FET's, reduction in gate length or channel length resulting from curtailment of occupation area has brought about an improvement in the operation speed.
However, recently, drastic reduction of gate length causes a new problem--the so-called "short channel" effect. This effect is such that the controllability of the conductivity between the source and drain of the IG FET by the gate is lost, such loss being in the form of a decrease in the threshold level of the MIS FET.
In order to realize the normal function of an integrated circuit, this short channel effect must, of course, be eliminated. Various measures have been attempted in an effort to eliminate the short channel effect without, at the same time, losing high-speed operational characteristics.
One of the most effective measures is to employ a so-called E/D gate structure. As is well known, the E/D gate type IG FET is characterized in that the enhancement mode operational area and the depletion mode operational area are disposed in series between the source and drain areas under the single gate electrode. Such an IG FET has a channel length which is substantially shorter than that of the other IG FET's having the same electrode length (since switching speed is related to or a function of enhancement mode area), and such an IG FET also has a high speed operational characteristic. Moreover, since the distance between the source and drain areas is comparatively long due to existence of the depletion mode area, such an arrangement does not easily result in the short channel effect, and has a high punch-through voltage.
On the other hand, the E/D gate type IG FET having very short enhancement mode area often experiences difficulty in manufacturing. This is due to the fact that addition of a highly accurate masking step is generally required for adding the depletion mode operational area to the gate structure. In the usual case, the depletion mode area is formed by a process whereby an impurity is selectively injected (e.g., by ion implantation) while the enhancement mode area is masked. Thus, the manufacturing process as a whole becomes complicated and, in addition, high grade lithographic technology is required for the masking of the minute enhancement mode area.
As an example of an E/D gate type IG FET which can be manufactured without any particular additional masking step, the so-called V-type MOSFET (VMOS)--for example, as disclosed in U.S. Pat. No. 4,003,036--is now considered. In the VMOS, the gate structure is formed along the surface of a V-shaped recess which extends into the device to such a depth as to pass through the epitaxial layer of the semiconductor substrate, and simultaneously the enhancement mode area is constituted by an interface layer which is formed by impurity diffusion into the epitaxial layer from the substrate. On the other hand, the depletion mode area is constituted by the remaining epitaxial layer. Namely, the depletion mode channel length and enhancement mode channel length are determined in accordance with the thickness of the epitaxial layer and the thickness of the interface layer formed by the impurity diffusion. As is well known, depth of impurity diffusion and thickness of the epitaxial layer can be controlled with comparative ease and with higher accuracy in the VMOS case, as compared with the lithographic case. Thus, the VMOS easily realizes a very short effective channel without need for the additional masking step and the difficult lithographic technology.
However, the VMOS mentioned above has several serious disadvantages, particularly in applications involving logic circuits. That is, in a logic circuit configuration employing an IG FET, it is generally required that the electrode wiring layer come into contact with the source region, but that is difficult to achieve in the VMOS. This is because the storage capacitor region (corresponding to the source region) is composed of a buried N.sup.+ layer formed within the semiconductor substrate. Moreover, such a VMOS exhibits a comparatively high punch-through voltage when a higher positive voltage for the buried N.sup.+ layer is applied to the N.sup.+ region disposed on the substrate surface, but exhibits a low punch-through voltage when a voltage is applied in the reverse direction.
In an application involving logic circuitry, the VMOS can be modified in such a manner that the substrate and the epitaxial layer thereon have mutually opposite conductivity types, and the substrate functions as a common source region. In such a case, the source electrode becomes unnecessary, and difficulty of formation of such an electrode can thereby be eliminated. However, configuration of such logic circuitry so that different voltages are given to several sources is not possible.